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74als373/74als374 latch/flipflop product specification ic05 data handbook 1991 feb 08 integrated circuits
philips semiconductors product specification 74als373/74als374 latch/flip-flop 74als373 octal transparent latch (3-state) 74als374 octal d flip-flop (3-state) 2 1991 feb 08 8531243 01670 features ? 8-bit transparent latch 74als373 ? 8-bit positive edge triggered register 74als374 ? 3-state output buffers ? common 3-state output register ? independent register and 3-state buffer operation type typical propagation delay typical supply current (total) 74als373 6.0ns 14ma type typical f max typical supply current (total) 74als374 50mhz 17ma ordering information order code description commercial range v cc = 5v 10%, t amb = 0 c to +70 c drawing number 20-pin plastic dip 74als373n, 74ALS374N sot146-1 20-pin plastic sol 74als373d, 74als374d sot163-1 20-pin plastic ssop type ii 74als373db, 74als374db sot339-1 description the 74als373 is an octal transparent latch coupled to eight 3-state output devices. the two sections of the device are controlled independently by enable (e) and output enable (oe ) control gates. the data on the d inputs is transferred to the latch outputs when the enable (e) input is high. the latch remains transparent to the data input while e is high, and stores the data that is present one setup time before the high-to-low enable transition. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active-low output enable (oe) controls all eight 3-state buffers independent of the latch operation. when oe is low, latched or transparent data appears at the output. when oe is high, the outputs are in high impedance aoffo state, which means they will neither drive nor load the bus. the 74als374 is an 8-bit edge triggered register coupled to eight 3-state output buffers. the two sections of the device are controlled independently by clock (cp) and output enable (oe) control gates. the register is fully edge triggered. the state of the d input, one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop's q output. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active-low output enable (oe) controls all eight 3-state buffers independent of the register operation. when oe is low, the data in the register appears at the outputs. when oe is high, the outputs are in high impedance aoffo state, which means they will neither drive nor load the bus. input and output loading and fan-out table pins description 74als (u.l.) high/low load value high/low d0 d7 data inputs 1.0/1.0 20 m a/0.1ma e (74als373) enable input (active-high) 1.0/1.0 20 m a/0.1ma oe output enable inputs (active-low) 1.0/1.0 20 m a/0.1ma cp (74als374) clock pulse input (active rising edge) 1.0/1.0 20 m a/0.1ma q0 q7 3-state outputs 130/240 2.6ma/24ma note: one (1.0) als unit load is defined as: 20 m a in the high state and 0.1ma in the low state.
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 3 pin configuration 74als373 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 oe q0 d0 d1 q1 q2 d2 d3 q3 gnd v cc q7 d7 d6 q6 q5 d5 d4 q4 e sf00250 pin configuration 74als374 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 oe q0 d0 d1 q1 q2 d2 d3 q3 gnd v cc q7 d7 d6 q6 q5 d5 d4 q4 cp sf00253 logic symbol 74als373 e q0 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 v cc = pin 20 gnd = pin 10 11 1 oe sf00251 logic symbol 74als374 cp q0 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 v cc = pin 20 11 1 gnd = pin 10 oe sf00254 iec/ieee symbol 74als373 1 en2 2d en1 1 11 3 4 7 8 13 14 17 18 2 5 6 12 9 15 16 19 sf00252 iec/ieee symbol 74als374 1 c1 2d en1 1 11 3 4 7 8 13 14 17 18 2 5 6 12 9 15 16 19 sc00098
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 4 logic diagram 74als373 v cc = pin 20 gnd = pin 10 d0 d e q q0 3 2 d1 d e q q1 4 5 d2 d e q q2 7 6 d3 d e q q3 8 9 d4 d e q q4 13 12 d5 d e q q5 14 15 d6 d e q q6 17 16 d7 d e q q7 18 19 11 1 e oe sf00256 function table 74als373 inputs internal register outputs operating mode oe e dn internal register q0 q7 operating mode l h l l l enable and read register l h h h h enable and read register l l l l latch and read register l h h h latch and read register l l x nc nc hold h l x nc z disable out p uts h h dn dn z disable o u tp u ts h = high-voltage level h = high state must be present one setup time before the high-to-low enable transition l = low-voltage level l = low state must be present one setup time before the high-to-low enable transition nc= no change x = don't care z = high impedance aoffo state = high-to-low enable transition
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 5 logic diagram 74als374 v cc = pin 20 d0 d cp q q0 3 2 d1 d cp q q1 4 5 d2 d cp q q2 7 6 d3 d cp q q3 8 9 d4 d cp q q4 13 12 d5 d cp q q5 14 15 d6 d cp q q6 17 16 d7 d cp q q7 18 19 11 1 oe cp gnd = pin 10 sf00257 function table 74als374 inputs internal register outputs operating mode oe cp dn internal register q0 q7 operating mode l l l l load and read register l h h h load and read register l x nc nc hold h x nc z disable out p uts h dn dn z disable o u tp u ts h = high-voltage level h = high state must be present one setup time before the low-to-high clock transition l = low-voltage level l = low state must be present one setup time before the low-to-high clock transition nc= no change x = don't care z = high impedance aoffo state = low-to-high clock transition = not low-to-high clock transition absolute maximum ratings (operation beyond the limit set forth in this table may impair the useful life of the device. unless otherwise noted these limits are over the operating free-air temperature range.) symbol parameter rating unit v cc supply voltage 0.5 to +7.0 v v in input voltage 0.5 to +7.0 v i in input current 30 to +5 ma v out voltage applied to output in high output state 0.5 to v cc v i out current applied to output in low output state 48 ma t amb operating free-air temperature range 0 to +70 c t stg storage temperature range 65 to +150 c
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 6 recommended operating conditions symbol parameter limits unit symbol parameter min nom max unit v cc supply voltage 4.5 5.0 5.5 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ik input clamp current 18 ma i oh high-level output current 2.6 ma i ol low-level output current 24 ma t amb operating free-air temperature range 0 +70 c dc electrical characteristics (over recommended operating free-air temperature range unless otherwise noted.) symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min typ 2 max unit v o high level out p ut voltage v cc = 10%, v il = max, i oh = 0.4ma v cc 2 v v oh high - le v el o u tp u t v oltage cc , il , v ih = min i oh = max 2.4 3.2 v v o low level out p ut voltage v cc = min, v il = max, i ol = 12ma 0.25 0.40 v v ol lo w- le v el o u tp u t v oltage cc , il , v ih = min i ol = 24ma 0.35 0.50 v v ik input clamp voltage v cc = min, i i = i ik 0.73 1.2 v i i input current at maximum input voltage v cc = max, v i = 7.0v 0.1 ma i ih high-level input current v cc = max, v i = 2.7v 20 m a i low-level input 74als373 v cc = max v =04v 0.1 ma i il current 74als374 v cc = max , v i = 0 . 4v 0.2 ma i ozh off-state output current, high-level voltage applied v cc = max, v i = 2.7v 20 m a i ozl off-state output current, low-level voltage applied v cc = max, v i = 0.4v 20 m a i o output current 3 v cc = max, v o = 2.25v 30 112 ma i cch 7 16 ma 74als373 i ccl v cc = max 14 25 ma i cc su pp ly current (total) i ccz 17 27 ma i cc s u ppl y c u rrent (total) i cch 11 19 ma 74als374 i ccl v cc = max 19 29 ma i ccz 20 31 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applic able type. 2. all typical values are at v cc = 5v, t amb = 25 c. 3. the output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit outp ut current, i os .
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 7 ac electrical characteristics limits symbol parameter test condition t amb = 0 c to +70 c v cc = +5.0v 10% c l = 50pf, r l = 500 w unit min max t plh t phl propagation delay dn to qn waveform 3 2.0 2.0 12.0 14.0 ns t plh t phl propagation delay e to qn 74als373 waveform 2 3.0 3.0 14.0 14.0 ns t pzh t pzl output enable time to high or low level 74als373 waveform 6 waveform 7 2.0 3.0 14.0 14.0 ns t phz t plz output disable time from high or low level waveform 6 waveform 7 2.0 2.0 10.0 12.0 ns f max maximum clock frequency waveform 1 50 mhz t plh t phl propagation delay cp to qn waveform 1 3.0 4.0 12.0 14.0 ns t pzh t pzl output enable time to high or low level 74als374 waveform 6 waveform 7 3.0 3.0 9.0 11.0 ns t phz t plz output disable time from high or low level waveform 6 waveform 7 2.0 3.0 10.0 12.0 ns ac setup requirements limits symbol parameter test condition t amb = 0 c to +70 c v cc = +5.0v 10% c l = 50pf, r l = 500 w unit min max t su (h) t su (l) setup time, high or low dn to e waveform 4 6.0 6.0 ns t h (h) t h (l) hold time, high or low dn to e 74als373 waveform 4 6.0 6.0 ns t w (h) e pulse width, high waveform 2 10.0 ns t su (h) t su (l) setup time, high or low dn to cp waveform 5 6.0 6.0 ns t h (h) t h (l) hold time, high or low dn to cp 74als374 waveform 5 1.0 1.0 ns t w (h) t w (l) cp pulse width, high or low waveform 1 10.0 10.0 ns
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 8 ac waveforms for all waveforms, v m = 1.3v. the shaded areas indicate when the input is permitted to change for predictable output performance. cp v m v m v m t w (h) 1/f max v m v m t phl t w (l) t plh qn sf00258 waveform 1. propagation delay for clock input to output, clock pulse widths, and maximum clock frequency t phl ev m v m v m t w (h) v m v m q n t plh sf00259 waveform 2. propagation delay for enable to output and enable pulse width dn v m v m v m v m t phl t plh qn sf00260 waveform 3. propagation delay for data to output v m v m v m v m v m v m t su (l) t h (l) t su (h) t h (h) e dn sf00261 waveform 4. data setup time and hold times v m v m v m v m v m v m t su (l) t h (l) t su (h) t h (h) cp dn sf00262 waveform 5. data setup time and hold times v m v m v m t phz t pzh oe qn v oh -0.3v 0v sc00099 waveform 6. 3-state output enable time to high level and output disable time from high level v m v m v m t plz t pzl oe qn v ol +0.3v sc00100 3.5v waveform 7. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74als373/74als374 latch/flip-flop 1991 feb 08 9 test circuit and waveforms t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0.3v 0.3v t thl ( t f f ) input pulse requirements rep.rate t w t tlh t thl 1mhz 500ns 2.0ns 2.0ns input pulse definition v cc family 74als d.u.t. pulse generator r l c l r t v in v out test circuit for 3-state outputs definitions: r l = load resistor; see ac electrical characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac electrical characteristics for value. r t = termination resistance should be equal to z out of pulse generators. t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.5v 1.3v v m sc00072 r l 7.0v switch position test switch t plz , t pzl closed all other open
philips semiconductors product specification 74als373/74als374 latch/flipflop 1991 feb 08 10 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
philips semiconductors product specification 74als373/74als374 latch/flipflop 1991 feb 08 11 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product specification 74als373/74als374 latch/flipflop 1991 feb 08 12 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
philips semiconductors product specification 74als373/74als374 latch/flipflop 1991 feb 08 13 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. ? copyright philips electronics north america corporation 1997 all rights reserved. printed in u.s.a.

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